If PC is 84 when an interrupt is detected, the address of the next instruction executed is 4000.
The very next instruction executed after detecting an interrupt is located at location 4000. This is because the ISR instructions are located at 4000, and the CPU jumps to the ISR commands when an interrupt is detected.
The eret instruction returns the CPU to the instruction at address 84 once the ISR instructions have handled the interrupt. Consequently, when an interrupt is detected, the following instruction is performed at 4000.
The address of the next instruction to be executed is 4000 if the interrupt is handled using the eret instruction.
Initial instruction of interrupt service procedure is at this location (ISR). if the interrupt isn't handled with an eret, then address 84, the instruction after the 1w instruction, will be executed.
When an interrupt is detected, the PC is set to the first instruction in the interrupt service method (ISR). A modification to the PC will not be made if the interrupt is not dealt with using the eret instruction.
Instead, the instruction after the 1w instruction is executed. An interrupt handler's eret instruction sets the following instruction's address to 4000. Its original instruction is located at this location (ISR).
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