Design the State Generator:
State Generator: The State Generator should be designed to cycle through each state of the operation. Since these are 4-bit numbers, the operation will use 6 clock cycles, Load R1, Load R2, and 4 shift operations. Consult the ASM chart later in this document for details on the states.
State Generator Behavior:
Hold in the initial state (T0) until START is set to 1
Move through the remaining 5 states and return to T0 when completed.
The value of START does not matter while in states 1-5
Asynchronously return to the initial state (T0) when the system RESET is '0'
See the State Generator in Chapter 11 of the textbook as an example.
State Generator Hardware:
For the state generator you should use 6 States with 1-hot encoding.
You can utilize the following chips:
Unlimited AND, OR, NOT, XOR, XNOR Gates
6 DFF
State Gen Inputs: State Gen Outputs:
RESET : active-low reset T[0..5] : present state
that sets the state generator to T0
START : Start Command
clk : system clock