It is desired to design a modulo-6 counter circuit that counts repeatedly through the length- 6 sequence of decimal numbers in that order:
[0,4,5,2,3,1,â¦]
Using three D-flip-flops, Q2 ,Q 1 ,Q 0 , with Q 2 representing the most-significant-bit of the decimal sequence and Q 0, the least-significant-bit, show that the required next-state flip-flop excitation equations for the counter will be as follows, where you only need to determine the correct expression for
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