the starting address of matrix a, b, and c are 0x8000 7f80, 0x8000 8000, and 0x8000 8080, respectively. all elements are integers (4 bytes in size), both virtual and physical addresses are 32-bits, and assume there is no cache prefetching. answer the following questions. 1. (20 points) the data cache is direct mapped, has 64 sets, and each cache line holds 16b. it uses a write-back policy and is virtually indexed and virtually tagged. assuming that the cache is initially empty, how many cache misses occur? 2. (15 points) if the cache were to be physically indexed and physically tagged, then the address is translated from virtual to physical before accessing the cache. given a page size of 4kib and a fully-associative translation lookaside buffer (tlb) of 64 entries, how many tlb misses occur? assume that the tlb is initially empty. 3. (15 points) if the page size were to be 1mib, then how many page faults would occur? assume that the page table is single-level, and all the pages for the three matrices are not in memory.